MT47H128M8JN-3LHTR 查看數據表（PDF） - Micron Technology
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MT47H128M8JN-3LHTR Datasheet PDF : 133 Pages
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1Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
Table 10: DDR2 IDD Specifications and Conditions (Die Revision H)
Notes: 1–7 apply to the entire table
Parameter/Condition
Operating one bank active-
precharge current: tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH be-
tween valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating one bank active-read-precharge cur-
rent: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK =
tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are switching; Data
pattern is same as IDD4W
Precharge power-down current: All banks idle; tCK
= tCK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Precharge quiet standby
current: All banks idle; tCK = tCK (IDD); CKE is HIGH,
CS# is HIGH; Other control and address bus inputs are
stable; Data bus inputs are floating
Precharge standby current: All banks idle; tCK = tCK
(IDD); CKE is HIGH, CS# is HIGH; Other control and ad-
dress bus inputs are switching; Data bus inputs are
switching
Active power-down current: All banks open; tCK =
tCK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Active standby current: All banks open; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All banks open, con-
tinuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK =
tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switch-
ing
Operating burst read current: All banks open, con-
tinuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, CS# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus in-
puts are switching
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3Pf
IDD3Ps
IDD3N
IDD4W
IDD4R
Configuration
x4, x8
x16
x4, x8
x16
x4, x8, x16
x4, x8
x16
x4, x8
x16
Fast exit
MR12 = 0
Slow exit
MR12 = 1
x4, x8
x16
x4 ,x8
x16
x4, x8
x16
-187E
75
90
85
100
7
28
30
34
36
23
10
40
42
145
185
140
180
-25E
65
80
75
95
7
24
26
28
30
20
10
33
35
125
160
120
150
-3
Units
60
mA
75
70
mA
90
7
mA
24
mA
26
24
mA
26
15
mA
10
30
mA
32
115
mA
135
110
mA
125
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
28
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