MC74HC161AD 查看數據表（PDF） - ON Semiconductor

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MC74HC161AD

8-Bit Serial or Parallel-Input/Serial-Output Shift Register

ON Semiconductor 

MC74HC161A, MC74HC163A

TYPICAL APPLICATIONS CASCADING

LOAD

INPUTS

INPUTS

INPUTS

H = COUNT

L = DISABLE

H = COUNT

L = DISABLE

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

TO

MORE

SIGNIFICANT

STAGES

RESET

CLOCK

OUTPUTS

OUTPUTS

OUTPUTS

NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on

number of stages. This limitation is due to set up times between Enable (Port) and Clock.

Figure 11. N–Bit Synchronous Counters

LOAD

ENABLE P

ENABLE T

CLOCK

RESET

INPUTS

INPUTS

INPUTS

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

LOAD P0 P1 P2 P3

ENABLE P

ENABLE T

CLOCK

RIPPLE

CARRY

OUT

R Q0 Q1 Q2 Q3

TO

MORE

SIGNIFICANT

STAGES

OUTPUTS

OUTPUTS

Figure 12. Nibble Ripple Counter

OUTPUTS

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