MAX9205(2001) 查看數據表（PDF） - Maxim Integrated

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MAX9205
(Rev.:2001)

10-Bit Bus LVDS Serializers

Maxim Integrated 

10-Bit Bus LVDS Serializers

PWRDN

2.0V

TCLK

tPL

1.5V

tZH OR tZL

OUT±

HIGH IMPEDANCE

SYNC 1 = SYNC 2 = LOW

EN = HIGH

TCLK_R/F = HIGH

Figure 7. PLL Lock Time and PWRDN High-Impedance Delays

ACTIVE

0.8V

tHZ OR tLZ

HIGH IMPEDANCE

IN

TCLK

IN0 - IN9 SYMBOL N

tSD

1.5V

IN0 - IN9 SYMBOL N + 1

OUT±

TCLK_ R/F = HIGH

TIMING SHOWN FOR TCLK_R/F = HIGH

START BIT OUT0 - OUT9 SYMBOL N

STOP BIT START BIT

OUT0 - OUT9 SYMBOL N+1

VDIFF = 0

VDIFF = (OUT+) - (OUT-)

Figure 8. Serializer Delay

STOP BIT

(OUT+) - (OUT-)

WAVEFORM

O DIFFERENTIAL

tDJIT

SUPERIMPOSED RANDOM DATA

Figure 9. Definition of Deterministic Jitter (tDJIT)

tRJIT

tRJIT

"CLOCK" PATTERN (1010...)

Figure 10. Definition of Random Jitter (tRJIT)

(OUT+) - (OUT-)

WAVEFORM

O DIFFERENTIAL

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