MAX1213EGK(2004) 查看數據表（PDF） - Maxim Integrated

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MAX1213EGK
(Rev.:2004)

1.8V, 12-Bit, 170Msps ADC for Broadband Applications

Maxim Integrated 

1.8V, 12-Bit, 170Msps ADC for

Broadband Applications

PIN

1, 6, 11–14, 20,

25, 62, 63, 65

2, 5, 7, 10, 15, 16,

18, 19, 21, 24,

64, 66, 67

3

4

8

9

17

22

23

26, 45, 61

27, 28, 41, 44, 60

29

30

31

32

33

34

35

36

NAME

AVCC

AGND

REFIO

REFADJ

INP

INN

CLKDIV

CLKP

CLKN

OGND

OVCC

D0N

D0P

D1N

D1P

D2N

D2P

D3N

D3P

Pin Description

FUNCTION

Analog Supply Voltage. Bypass each pin with a parallel combination of 0.1µF and 0.22µF

capacitors for best decoupling results.

Analog Converter Ground

Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference

source to be connected to the MAX1213. With REFADJ pulled low, the internal 1.24V bandgap

reference is active.

Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim

potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases

FSR). If REFADJ is connected to AVCC, the internal reference can be overdriven with an

external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is

used to determine the FSR of the data converter.

Positive Analog Input Terminal

Negative Analog Input Terminal

Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s

digital outputs are updated with. CLKDIV has an internal pulldown resistor.

CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.

CLKDIV = 1: ADC updates digital outputs at input clock rate.

True Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the

converter’s excellent performance.

Complementary Clock Input. This input ideally requires an LVPECL-compatible input level to

maintain the converter’s excellent performance.

Digital Converter Ground. Ground connection for digital circuitry and output drivers.

Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.

Complementary Output Bit 0 (LSB)

True Output Bit 0 (LSB)

Complementary Output Bit 1

True Output Bit 1

Complementary Output Bit 2

True Output Bit 2

Complementary Output Bit 3

True Output Bit 3

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