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MAX1180 查看數據表(PDF) - Maxim Integrated

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MAX1180 Datasheet PDF : 21 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Dual 10-Bit, 105Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kresistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 105.263MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output Supply Current
Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse-Width High
IOVDD
PDISS
PSRR
Operating, CL = 15pF , fINA or B = 20MHz at
-0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA or B = 20MHz at -0.5dBFS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
tDO
tENABLE
tDISABLE
Figure 3 (Note 5)
Figure 4
Figure 4
tCH Figure 3, clock period: 9.5ns
15
mA
100
µA
2
10
413
511
mW
9.2
µW
3
50
±0.2
mV/V
±0.1
%/V
5
8
ns
10
ns
1.5
ns
4.75
±1.5
ns
CLK Pulse-Width Low
tCL
Figure 3, clock period: 9.5ns
4.75
±1.5
ns
Wake-Up Time (Note 6)
tWAKE
Wakeup from sleep mode
Wakeup from shutdown
0.18
µs
1.5
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
fINA or B = 20MHz at -0.5dBFS
fINA or B = 20MHz at -0.5dBFS
-70
dB
0.02 ±0.2
dB
Phase Matching
fINA or B = 20MHz at -0.5dBFS
0.25
degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS, referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________ 5

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