MAX11206EEE 查看數據表（PDF） - Maxim Integrated

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MAX11206EEE

20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO

Maxim Integrated 

MAX11206/MAX11207

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Serial-Digital Interface

The MAX11206/MAX11207 interface is fully compatible

with SPI-, QSPI-, and MICROWIRE-standard serial inter-

faces. The SPI interface provides access to nine on-chip

registers that are 8 or 24 bits wide.

Drive CS low to transfer data in and out of the devices.

Clock in data at DIN on the rising edge of SCLK. The

RDY/DOUT output serves two functions: conversion sta-

tus and data read. To find the conversion status, assert

CS low and read the RDY/DOUT output; the conversion

is in progress if the RDY/DOUT output reads logic-high

and the conversion is complete if the RDY/DOUT output

reads logic-low. Data at RDY/DOUT changes on the

falling edge of SCLK and is valid on the rising edge of

SCLK. DIN and DOUT are transferred MSB first. Drive

CS high to force DOUT high impedance and cause the

devices to ignore any signals on SCLK and DIN. Figures

5, 6, and 7 show the SPI timing diagrams.

tCSH0

tCSS0

CS

SCLK

0

1

tDS

tDH

tCP

tCL tCH

tCSH1

tCSW

tCSS1

8

DIN

X

1

tDOE

HIGH-Z

RDY/DOUT

Figure 5. SPI Command Byte

0

CAL1

CAL0

IMPD RATE2 RATE1 RATE0

tDOD

HIGH-Z

SPI REGISTER ACCESS WRITE

tCSH0

tCSS0

CS

SCLK 0

1

tDS

tDH

tCP

tCL

tCH

8

9

tCSW

tCSH1

tCSS1

16

DIN X

HIGH-Z

RDY/DOUT

1

1

tDOE

X RS3 RS2 RS1 RS0 W/R D7 D6 D5 D4 D3 D2 D1 D0

Figure 6. SPI Register Access Write

tDOD

HIGH-Z

14  

Maxim Integrated

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