10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Pin Description
PIN
MAX1030 MAX1030 MAX1028 MAX1026
TQFN
QSOP
1, 17, 19,
—
—
—
25
2–12, 26,
1–14
—
—
27, 28
—
—
1–10
—
—
—
—
1–6
13
15
—
—
—
—
11
—
—
—
—
7
14
16
—
—
—
—
12
—
—
—
—
8
15
17
13
9
16
18
14
10
18
19
15
11
20
20
16
12
21
21
17
13
22
22
18
14
23
23
19
15
24
24
20
16
—
—
—
—
NAME
FUNCTION
N.C.
No Connection. Not internally connected.
AIN0–13 Analog Inputs
AIN0–9
AIN0–5
Analog Inputs
Analog Inputs
REF-/AIN14
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
REF-/AIN10
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
CNVST/
AIN11
CNVST/
AIN7
REF+
GND
VDD
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF capacitor.
SCLK
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
CS
Active-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
DIN
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
DOUT
EOC
EP
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to VDD.
End of Conversion Output. Data is valid after EOC pulls low.
Exposed Pad (TQFN Only). Connect EP to GND.
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