MAS3549F 查看數據表（PDF） - Micronas

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MAS3549F

MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec

Micronas 

MAS 35x9F

DATA SHEET

Table 3–3: Direct configuration registers

I2C Sub-

address

(hex)

Function

6A

Control Register (reset value = 3000hex)

bit[15:14] Analog supply voltage range

Code

00

01

10

11

AGNDC

1.1 V

1.3 V

1.6 V

reserved

recommended for voltage range of AVDD

2.0 ... 2.4 V (reset)

2.4 ... 3.0 V

3.0 ... 3.6 V

reserved

Higher voltage ranges permit higher output levels and thus a better signal-to-

noise ratio.

bit[13]

bit[12]

Enable DC/DC 2 (reset=1)

Enable DC/DC 1 (reset=1)

Both DC/DC converters are switched on by default with DCEN = high (1).

bit[11]

bit[10]

Enable and reset audio codec2)

Enable and reset DSP core2)

For normal operation (MPEG-decoding and D/A conversion), both, the DSP

core and the audio codec have to be enabled after the power-up procedure.

The DSP can be left off if an audio signal is routed from the analog inputs to

the analog outputs (set bit[15] in codec register 00 0Fhex). The audio codec

can be left off if the DSP uses digital inputs and outputs only.

bit[9]

bit[8]

Reset codec

Reset DSP core

bit[7]

Enable crystal input clock divider of 1.5

(extended range up to 28 MHz)1)

bit[6:0]

Reserved, must be set to zero

1) refer to Section 4.6.3. on page 81

2) refer to Section 2.11.2.1.

Name

CONTROL

24

June 30, 2004; 6251-505-1DS

Micronas

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