11117-002 查看數據表（PDF） - AMI Semiconductor
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11117-002 Datasheet PDF : 8 Pages
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November 1998
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
P
VSS
Crystal Oscillator Ground
2
DO
CLK1
PLL 1 Clock Output
3
DIU
OE
Output Enable
4
P
VSS
Ground
5
AI
XIN
Crystal Oscillator Feedback
6
AO
XOUT
Crystal Oscillator Drive
7
DIU
SEL
Output Frequency Select
8
P
VDD
Power Supply (+5V)
9
P
VDD
Crystal Oscillator Power (+5V)
10
DO
CLKD
PLL D Clock Output
11
P
VSS
Ground
12
DO
CLKC
PLL C Clock Output
13
DO
CLK2
PLL 2 Clock Output
14
P
VDD
Power Supply (+5V)
15
DO
CLKB
PLL B Clock Output
16
DO
REF
Reference Oscillator Output
4.0 Functional Block Description Table 2: Output Frequencies
4.1 Phase-Locked Loops (PLLs)
Each one of the five on-chip PLLs in the FS6017 is a
standard frequency- and phase-locked loop architecture.
Each PLL multiplies the reference oscillator to the desired
frequency by a ratio of integers. The frequency multipli-
cation is exact.
4.2 Frequency Select (SEL)
Three of the PLLs can switch between one of two possi-
ble output frequencies depending on the logic state of the
SEL pin. The clock outputs that can be changed are the
CLKB, CLKC, and CLKD outputs. Note that the transi-
tions are not glitch-free.
The SEL pin defaults to a logic-high through an internal
pull-up.
OUTPUT CLOCK
SEL PIN
FREQUENCY (MHz)
CLK1
-
11.2896
CLK2
-
32.0000
1
CLKB
0
56.0000
64.0000
1
CLKC
0
40.0000
48.0000
1
CLKD
0
80.0000
3.6864
NOTE: Custom frequencies available – contact AMI for more information
4.3 Output Tristate Control (OE)
All clock outputs of the FS6017 may be tristated to facili-
tate circuit board testing. When the output enable (OE)
pin is low, all outputs are placed in a high-impedance
state and the outputs can neither drive nor load con-
nected lines.
By default, all the clock outputs are enabled through an
internal pull-up on the OE pin.
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11.20.98
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