LPD6803 查看數據表（PDF） - Unspecified

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LPD6803

3 channel constant-current driver and grey-level modulate output

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LPD6803 datasheet

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task, during this time, each LPD6803 will continue keeping original duty cycle

drive output(FREE-RUN mode), till MCU send out next updated data.

Notice: after all data are input in chip on the up-edge of DCLK, it may need

send more DCLK pulse (DIN=0), on principle, how many group point in the

transfer link, how many related pulse need to be sent out, it is important to

which later chip built-in PLL re-gernate circuit can work in gear.

To make LPD6803 produce more particularity grey level by less data, when

GMODE=0/

CMODE=0, built-in SUPER-PWM can change 5 bit data into non-line 256 grade grey

output, minimum open width is 1T, maxim open width is 256T ( T is grey clock

cycle)

When GMODE=1 or dangle , output is line 32 grade grey, minimum open width is 4T,

and maxim open width is 128T.

C51 example:

//SDO, SCLK is data and shift output, bit variability ,nDots is light qty

// this program is only suitable in GMODE=1,CMODE=1 situation.

// first output 32 “0” start frame

SCLK=0;

SD0=0,

For (i=0;i<32;i++){SCLK=1;SCLK=0;}

// then output nDots data, here suppose each point colour are(dr,dg,db)

//dr,db,dg is red, green and blue grey level 0-31

For (i=o;i<nDots;i++)

{ SD0=1;SCLK=1;SCLK=0;

//first output one “1” as start bit

//output 5 bits red data

Mask=0x10;

For (j=0;j<5;j++)

{ if (mask &dr) SD0=1;

Else

SD0=0;

SCLK=1; SCLK=0;

Mask>>=1; }

// output 5 bits green data

Mask=0x10;

For (j=0;j<5;j++)

{ if(mask &dg)SD0=1;

Else

SD0=0;

SCLK=1;SCLK=0;

Mask>>=1; }

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