MT6225 查看數據表（PDF） - Unspecified
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MT6225 Datasheet PDF : 377 Pages
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MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00
CONFG+0404
h
APB Bus Control Register
Bit 15 14 13 12 11 10 9
8
Name
APB
W6
APB APB APB APB APB
W4 W3 W2 W1 W0
Type
R/W
R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
APB_CON
7
6
5
4
3
2
1
0
APBR
APBR APBR APBR APBR APBR
6
4
3
2
1
0
R/W
R/W R/W R/W R/W R/W
1
1
1
1
1
1
This register is used to control the timing of Read Cycle and Write Cycle on APB Bus. Note that APB Bridge 5 is
different from other bridges. The access time is varied, and access is not completed until acknowledge signal from APB
slave is asserted.
APBR0-APBR6Read Access Time on APB Bus
0 1-Cycle Access
1 2-Cycle Access
APBW0-APBW6 Write Access Time on APB Bus
0 1-Cycle Access
1 2-Cycle Access
3.4 Direct Memory Access
3.4.1 General Description
A generic DMA Controller is placed on Layer 2 AHB Bus to support fast data transfers and to off-load the processor.
With this controller, specific devices on AHB or APB buses can benefit greatly from quick completion of data
movement from or to memory modules such as Internal System RAM or External SRAM. Such Generic DMA
Controller can also be used to connect any two devices other than memory module as long as they can be addressed in
memory space.
Figure 10 Variety Data Paths of DMA Transfers
Up to fourteen channels of simultaneous data transfers are supported. Each channel has a similar set of registers to be
configured to different scheme as desired. If more than fourteen devices are requesting the DMA resources at the
same time, software based arbitration should be employed. Once the service candidate is decided, the responsible
device driver should configure the Generic DMA Controller properly in order to conduct DMA transfers. Both
Interrupt and Polling based schemes in handling the completion event are supported. The block diagram of such
generic DMA Controller is illustrated in Figure 11.
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