MT6225 查看數據表（PDF） - Unspecified

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MT6225

GSM/GPRS Baseband Processor

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MT6225 GSM/GPRS Baseband Processor Data Sheet Revision 1.00

Ext

Bus External

Memory

Interface

System ROM

System RAM

Internal Memory

Controller

Arbiter

ARM7EJ-S

Interrupt

Controller

AHB Bus

APB

Bridge

MCU-DSP

Interface

USB

DMA

Controller

APB Bus

Peripheral

Peripheral

Figure 6 Block Diagram of the Micro-Controller Unit Subsystem in MT6225

3.1 Processor Core

3.1.1 General Description

The Micro-Controller Unit Subsystem in MT6225 is built up with a 32-bit RISC core, ARM7EJ-S that is based on Von

Neumann architecture with a single 32-bit data bus carrying both instructions and data. The memory interface of

ARM7EJ-S is totally compliant to AMBA based bus system. Basically, it can be connected to AHB Bus directly.

3.2 Memory Management

3.2.1 General Description

The processor core of MT6225, ARM7EJ-S, supports only memory addressing method for instruction fetch and data

access. It manages a 32-bit address space that has addressing capability up to 4GB. System RAM, System ROM,

Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space, as depicted in

Figure 7.

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