LTC2607I-1 查看數據表（PDF） - Linear Technology

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LTC2607I-1

16-/14-/12-Bit Dual Rail-to-Rail DACs with I2C Interface

Linear Technology 

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OPERATIO

LTC2607/LTC2617/LTC2627

Write Word Protocol for LTC2607/LTC2617/LTC1627

S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE A 3RD DATA BYTE A P

Input Word (LTC2607)

INPUT WORD

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2617)

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

Input Word (LTC2627)

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

2607 F03

Figure 3

Table 2

COMMAND*

C3 C2 C1 C0

0000

0001

0011

0100

1111

ADDRESS*

A3 A2 A1 A0

0 000

0 001

1 111

Write to Input Register

Update (Power Up) DAC Register

Write to and Update (Power Up)

Power Down

No Operation

DAC A

DAC B

All DACs

*Command and address codes not shown are reserved and should not be used.

Power-Down Mode

For power-constrained applications, the power-down mode

can be used to reduce the supply current whenever one or

both of the DAC outputs are not needed. When in power-

down, the buffer amplifiers, bias circuits and reference input

are disabled and draw essentially zero current. The DAC out-

puts are put into a high impedance state, and the output pins

are passively pulled to VREFLO through 90k resistors.

Input-register and DAC-register contents are not disturbed

during power-down.

Either or both DAC channels can be put into power-down

mode by using command 0100b in combination with the

appropriate DAC address. The 16-bit data word is

ignored. The supply and reference currents are reduced

by approximately 50% for each DAC powered down; the

effective resistance at REF (Pin 9) rises accordingly,

becoming a high-impedance input (typically > 1GΩ)

when both DACs are powered down.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 2

or performing an asychronous update (LDAC) as

described in the next section. The selected DAC is powered

up as its voltage output is updated. When a DAC in

powered-down state is powered up and updated, normal

settling is delayed. If one of the two DACs is in a powered-

down state prior to the update command, the power up

delay is 5µs. If on the other hand, both DACs are powered

down, the main bias generation circuit has been automati-

cally shut down in addition to the DAC amplifiers and

reference input and so the power up delay time is

12µs (for VCC = 5V) or 30µs (for VCC = 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the

LDAC pin asynchronously updates the DAC registers with

the contents of the input registers. Asynchronous update

is disabled when the input word is being clocked into

the part.

26071727f

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