AD8197B 查看數據表（PDF） - Analog Devices
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AD8197B Datasheet PDF : 29 Pages
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AD8197B
PARALLEL INTERFACE CONFIGURATION REGISTERS
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and
PP_OCL pins. This interface is accessible only after the part is reset and before any registers are accessed using the serial control interface.
Because most systems use serial control for the input termination resistors, the parallel control interface is limited to controlling the
AD8197B status after reset and before serial logic control. The state of each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0).
Table 18. Parallel Interface Register Map
Name
Bit 7 Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
High Speed Device
Modes
High speed
switch enable
High speed source select
PP_EN
0
0
0
0
PP_CH[1]
PP_CH[0]
Auxiliary Device
Modes
Auxiliary switch
enable
Auxiliary switch source select
1
0
0
0
0
PP_CH[1]
PP_CH[0]
Receiver Settings
Input term.
select
(terminations
always open in
parallel control
mode)
1
Input Termination
Resistor Control.1
0
Source A and Source B input termination select (No parallel control termination, always open)
0
0
0
0
0
0
0
Input Termination
Resistor Control 2
0
Source C and Source D input termination select (No parallel control termination, always open)
0
0
0
0
0
0
0
Receive Equalizer 1
Source A and Source B input equalization level select
PP_EQ PP_EQ
PP_EQ PP_EQ PP_EQ
PP_EQ
PP_EQ
PP_EQ
Receive Equalizer 2
Source C and Source D input equalization level select
PP_EQ PP_EQ
PP_EQ PP_EQ PP_EQ
PP_EQ
PP_EQ
PP_EQ
Transmitter Settings
Output pre-emphasis Output termination Output current
level select
on/off select
level select
PP_PE[1] PP_PE[0] PP_OTO
PP_OCL
Rev. 0 | Page 21 of 28
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