ICS527R-01IT 查看數據表（PDF） - Integrated Circuit Systems
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ICS527R-01IT Datasheet PDF : 8 Pages
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ICS527-01
Clock Slicer™
User Configurable Zero Delay Buffer
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. A SYNC pulse is desired and the
1x output drive is selected.
VDD
0.01 µF
40 MHz
R5
R6
DIV2
S0
S1
VDD
ICLK
FBIN
GND
OECLK2
2XDRIVE
F0
F1
F2
R4
R3
R2
R1
R0
VDD
CLK1
CLK2
GND
PDTS
F6
F5
F4
F3
0.01 µF
33Ω
33Ω
50 MHz
SYNC
Note that the feedback is done AFTER the series termination resistor.
This will give the following waveforms:
40 MHz ICLK
50 MHz CLK1
SYNC CLK2
MDS 527-01 B
5
Revision 020801
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