LC7152M 查看數據表（PDF） - SANYO -> Panasonic

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LC7152M

Universal Dual-PLL Frequency Synthesizers

SANYO -> Panasonic 

LC7152, 7152M, 7152NM, 7152KM

Description of Serial Data

No.

(1)

. Controller/Data

Side-A

Description

This data sets the side-A programmable divider number. This data is a

Related Data

programmable

divider data: DA0

binary value in which DA0 is the LSB.

The range of divider values that can be set is 272 to 65,535.

R0 to R13

to DA15

(2) Side-B

. NA = fVCO-A/fref

This data sets the side-B programmable divider number. This data is a

programmable

divider data: DB0

binary value in which DB0 is the LSB.

The range of divider values that can be set is 272 to 65,535.

R0 to R13

to DB15

(3) Reference

. NB = fVCO-B/fref

This data sets the reference divider number. This data is a binary value in

frequency data: R0 which R0 is the LSB.

to R13

The range of divider values that can be set is 8 to 16,383.

UL0 Ul1 UE0 UE1

(Actual divider number) = (setting) x 2

(4)

Output port data:

. (reference frequency: fref) = (fX’tal: XIN)/(actual divider number)

This data determines the output on the general-purpose output port.

OA, OB

(5) Input frequency

OA → OUTA

OB → OUTB

. Data 0: open; Data 1: low

. During the power-on reset in the LC7152NM, OA and OB are both ‘‘0’’.

. This data switches the input frequency range for the PIA and PIB pins.

range switching

data: FA, FB

(FA → PIA, FB → PIB)

Data

[0]

Supply voltage (VDD)

2.0 to 3.3 V

1.5 to 23 MHz

DA0 to DA15

DB0 to DB15

[1]

20 to 55 MHz

(6)

.. Standby mode data

. : SB

In the case of the LC7152KM: Data 1: 55 to 80 MHz (VDD = 2.7 V to 3.3 V)

This data puts the PLL in standby mode.

SB = 1: standby mode (LDB pin: open)

. → Single PLL operation: Side-A operating, side-B stopped

SB = 0: standby mode off

(7)

Unlock detection

→ Dual PLL operation: Side-A operating, side-B operating

. During the power-on reset in the LC7152NM, SB is ‘‘1’’.

. This is the phase error detection threshold data that is used for PLL

data

lock/unlock discrimination. If the threshold shown in the table is exceeded,

the unlocked state is detected.

: UL0, UL1

Phase error

UL0 UL1 detector

threshold

00

0

10

±4/fX’tal

0 1 ±16/fX’tal

1 1 ±64/fX’tal

4.0

←

±1.00

±4.00

±16.00

unit : µs

XIN : fXIN [MHz] example

7.2

←

±0.55

±2.22

±8.88

8.0

←

±0.50

±2.00

±8.00

10.24

←

±0.39

±1.56

±6.25

12.8

←

±0.31

±1.20

±5.00

: UE0, UE1

(Note) Note that if the data changes in lock state, the PLL will be unlocked

temporarily.

. The detected phase error (øE) signal can be extended by a certain amount

of time and output on the LDA and LDB pins. This data determines the

length of this extension. However, when UL0 = UL1 = 0, the phase error is

not extended, and is output directly.

unit : ms

UE0 UE1

Reference

frequency

fref

Reference frequency :

fref [kHz] example

1 kHz

5 kHz 12.5 kHz

00

4 × (1/fref)

4.0*

0.8

0.32

10

8 × (1/fref)

8.0

1.6

0.64

0 1 32 × (1/fref)

32.0

6.4*

2.56

1 1 64 × (1/fref)

64.0

12.8

5.12*

(*standard value)

Continued on next page.

No.3889-8/13

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