SY100S317 查看數據表（PDF） - Micrel

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SY100S317

TRIPLE 2-WIDE OA/OAI GATE

Micrel 

Micrel, Inc.

TRIPLE 2-WIDE

OA/OAI GATE

SY100S317

SY100S317

FEATURES

DESCRIPTION

s Max. propagation delay of 900ps

s IEE min. of –48mA

s Extended supply voltage option:

VEE = –4.2V to –5.5V

s Voltage and temperature compensation for improved

noise immunity

s Internal 75KΩ input pull-down resistors

s Approximately 40% lower power than Fairchild

s Function and pinout compatible with Fairchild F100K

s Available in 24-pin CERPACK and 28-pin PLCC

packages

The SY100S317 is a set of ultra-fast, triple 2-wide OR/

AND gates designed for use in high-performance ECL

systems. This device offers both true and complement

outputs. The inputs on this device have 75KΩ pull-down

resistors.

BLOCK DIAGRAM

Ea

D1a

D2a

D3a

D4a

Eb

D1b

D2b

D3b

D4b

Ec

D1c

D2c

D3c

D4c

PIN NAMES

Pin

Function

Dna – Dnc

Data Inputs (n = 1...4)

Ea – Ec

Enable Inputs

Oa

Oa – Oc

Data Outputs

Oa

Oa – Oc

Complementary Data Outputs

VEES

VEE Substrate

VCCA

VCCO for ECL Outputs

Ob

Ob

Oc

Oc

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

1

Rev.: H Amendment: /0

Issue Date: March 2006

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