DDU8C3 查看數據表（PDF） - Data Delay Devices

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DDU8C3

5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE

Data Delay Devices 

DDU8C3

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

Ambient Temperature: 25oC ± 3oC

Supply Voltage (VDD): 3.3V ± 0.1V

Input Pulse:

High = 3.3V ± 0.1V

Low = 0.0V ± 0.1V

Source Impedance: 50Ω Max.

Rise/Fall Time:

3.0 ns Max. (measured

between 0.5V and 2.8V )

Pulse Width:

PWIN = 1.5 x Total Delay

Period:

PERIN = 10 x Total Delay

OUTPUT:

Load:

Cload:

Threshold:

1 CMOS Gate

5pf ± 10%

1.65V (Rising & Falling)

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

COMPUTER

SYSTEM

PRINTER

PULSE

GENERATOR

OUT

TRIG

IN DEVICE UNDER T1

TEST (DUT)

T2

T3

T4

T5

REF

IN

TRIG

TIME INTERVAL

COUNTER

Test Setup

TRISE

PWIN

PERIN

TFALL

INPUT

2.8V

VIH

2.8V

SIGNAL

1.5V

0.5V

1.5V

0.5V

VIL

TRISE

TFALL

OUTPUT

SIGNAL

VOH

1.5V

1.5V

VOL

Timing Diagram For Testing

Doc #00115

DATA DELAY DEVICES, INC.

4

5/19/00

Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com

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