SSTV16857 查看數據表（PDF） - Fairchild Semiconductor
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SSTV16857 Datasheet PDF : 7 Pages
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Functional Description
The SSTV16857 and SSTVN16587 are 14-bit registers
with SSTL-2 compatible inputs and outputs. Input data is
captured by the register on the positive edge crossing of
the differential clock pair.
When the LV-CMOS RESET signal is asserted LOW, all
outputs and internal registers are asynchronously placed
into the LOW logic state. In addition, the clock and data dif-
ferential comparators are disabled for power savings. Out-
put glitches are prevented by disabling the internal
registers more quickly than the input comparators. When
Logic Diagram
RESET is removed, the system designer must insure the
clock and data inputs to the device are stable during the
rising transition of the RESET signal.
The SSTL-2 data inputs transition based on the value of
VREF. VREF is a stable system reference used for setting
the trip point of the input buffers of the SSTV16857/
SSTVN16857 and other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the VREF signal.
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