CXA1616N 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

生产厂家

CXA1616N

Sync Discriminator for CRT Displays

Philips Electronics 

CXA1616N/S

Pin No.

Symbol Pin voltage

SDIP SSOP

Equivalent circuit

6 6 EHC

3.0, 4.8V

VCC

200

20k

6

1k

8k

1k

3.8V

12k

30µA 16k

VCC

8.3V

5.8V

4k

7

7 VIDEO IN 4.5V

200

7

29µA 16k

72k

Description

Connects a quasi-peak hold circuit

with a 33kΩ resistance and 0.22µF

capacitor to discriminate input signal

existence during composite sync input.

When there is a composite sync, the

voltage is held by the quasi-peak hold

circuit at 4.2 to 4.8V. This voltage is

then compared to a 3.8V reference

voltage, and an input signal is judged

to exist.

The voltage is 3.0V when no input

signal exists.

Inputs the sync-on video (sync is

negative polarity). Connect a 0.47µF

capacitor and a 270Ω resistance in

series between the pin and its signal

source.

The slice level is determined by the

relationship between the sync

frequency and Pulse width and the

sum of the 200Ω internal resistance

and the 270Ω external resistance

multiplied by the 29µA current.

∆V ≈ 29µA × (T2/T1) × (200 + 270)

4.5V

200k

70k

8 8 HD SEL

—

1k

8

9 9 TIMING

10.5V

VCC

100

10k

9

1k

30µA 17k

∆V

T1

T2

Selects whether or not to output the

VD interval portion of HD (H Drive

Pulse).

Input is at TTL Ievel.

V Low ≤ 0.5V

V High ≥ 2.0V

Low level: The VD interval HD is not

output.

High level or open: The VD interval HD

is output as is.

Connect a desired capacitor and a

12kΩ resistance in parallel to GND.

This capacitor changes the output

pulse width of clamp pulse.

(See Fig. 1)

–4–

Share Link: