ADSP-21060(RevH) 查看數據表（PDF） - Analog Devices

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ADSP-21060
(Rev.:RevH)

SHARC Processor

Analog Devices 

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

INTERNAL POWER DISSIPATION (3.3 V)

These specifications apply to the internal power portion of VDD

only. For a complete discussion of the code used to measure

power dissipation, see the technical note “SHARC Power Dissi-

pation Measurements.”

Specifications are based on the operating scenarios.

Operation

Instruction Type

Instruction Fetch

Core memory Access

Internal Memory DMA

Peak Activity (IDDINPEAK)

Multifunction

Cache

2 Per Cycle (DM and PM)

1 Per Cycle

High Activity (IDDINHIGH)

Multifunction

Internal Memory

1 Per Cycle (DM)

1 Per 2 Cycles

Low Activity (IDDINLOW)

Single Function

Internal Memory

None

1 Per 2 Cycles

To estimate power consumption for a specific application, use

the following equation where % is the amount of time your pro-

gram spends in that state:

%PEAK IDDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW +

%IDLE IDDIDLE = Power Consumption

Parameter

Test Conditions

Max

Unit

IDDINPEAK Supply Current (Internal)1

IDDINHIGH Supply Current (Internal)2

IDDINLOW Supply Current (Internal)2

IDDIDLE Supply Current (Idle)3

tCK = 30 ns, VDD = Max

tCK = 25 ns, VDD = Max

tCK = 30 ns, VDD = Max

tCK = 25 ns, VDD = Max

tCK = 30 ns, VDD = Max

tCK = 25 ns, VDD = Max

VDD = Max

540

mA

600

mA

425

mA

475

mA

250

mA

275

mA

180

mA

1 The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power

measurements made using typical applications are less than specified.

2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.

3 Idle denotes ADSP-2106xL state during execution of IDLE instruction.

Rev. H | Page 19 of 64 | March 2013

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