MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
13-Input NAND Gate
High–Performance Silicon–Gate CMOS
The MC74HC133 is identical in pinout to the LS133. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This NAND gate features 13 inputs which surpasses most random logic
requirements.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 68 FETs or 17 Equivalent Gates
LOGIC DIAGRAM
1
A
2
B
C3
D4
E5
6
F
G7
10
H
I 11
12
J
K 13
L 14
M 15
9
Y
Y = A•B•C•D•E•F•G•H•I•J•K•L•M
PIN 16 = VCC
PIN 8 = GND
MC74HC133
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
A1
B2
C3
D4
E5
F6
G7
GND 8
16 VCC
15 M
14 L
13 K
12 J
11 I
10 H
9Y
FUNCTION TABLE
Inputs A through M
All inputs H
All other combinations
Output
Y
L
H
10/95
© Motorola, Inc. 1995
1
REV 6