MT9160AS 查看數據表（PDF） - Mitel Networks
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MT9160AS Datasheet PDF : 28 Pages
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MT9160
Preliminary Information
20 PIN SOIC
VBias 1
VRef 2
PWRST 3
IC 4
A/µ/IRQ 5
VSSD 6
CS 7
SCLK 8
DATA1 9
DATA2 10
20 M +
19 M -
18 VSSA
17 HSPKR +
16 HSPKR -
15 VDD
14 CLOCKin
13 STB/F0i
12 Din
11 Dout
24 PIN PDIP
VBias 1
VRef 2
NC 3
PWRST 4
IC 5
A/µ/IRQ 6
VSSD 7
CS 8
NC 9
SCLK 10
DATA1 11
DATA2 12
24 M +
23 M -
22 VSSA
21 NC
20 HSPKR +
19 HSPKR -
18 VDD
17 CLOCKin
16 NC
15 STB/F0i
14 Din
13 Dout
Pin Description
Figure 2 - Pin Connections
Pin #
SOIC DIP
Name
Description
1
1
VBias Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to VSSA.
2
2
VRef
Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.5] volts. Used
internally. Connect 0.1 µF capacitor to VSSA.
3
4 PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
4
5
IC Internal Connection. Tie externally to VSS for normal operation.
5
6 A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec; µ-Law when tied to VSS and A-Law
when tied to VDD. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
6
7
VSSD Digital Ground. Nominally 0 volts.
7
8
CS Chip Select (Input). This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.
8 10 SCLK Serial Port Synchronous Clock (Input). Data clock for microport. TTL level
compatible.
9 11 DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input TTL level compatible.
10 12 DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.
7-78
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