M37702S1AFP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M37702S1AFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

M37702M2AXXXFP, M37702M2BXXXFP

M37702S1AFP, M37702S1BFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 2. Addresses of interrupt control registers

Interrupt control registers

Addresses

A-D conversion interrupt control register

00007016

UART0 transmit interrupt control register

00007116

UART0 receive interrupt control register

00007216

UART1 transmit interrupt control register

00007316

UART1 receive interrupt control register

00007416

Timer A0 interrupt control register

00007516

Timer A1 interrupt control register

00007616

Timer A2 interrupt control register

00007716

Timer A3 interrupt control register

00007816

Timer A4 interrupt control register

00007916

Timer B0 interrupt control register

00007A16

Timer B1 interrupt control register

00007B16

Timer B2 interrupt control register

____

INT0 interrupt control register

____

INT1 interrupt control register

____

INT2 interrupt control register

00007C16

00007D16

00007E16

00007F16

Interrupts caused by a BRK instruction and when dividing by zero

are software interrupts and are not included in this list.

Other interrupts previously mentioned are A-D converter, UART,

Timer, INT interrupts. The priority of these interrupts can be

changed by changing the priority level in the corresponding inter-

rupt control register by software.

Figure 8 shows a diagram of the interrupt priority resolution circuit.

When an interrupt is caused, the each interrupt device compares

its own priority with the priority from above and if its own priority is

higher, then it sends the priority below and requests the interrupt.

If the priorities are the same, the one above has priority.

This comparison is repeated to select the interrupt with the highest

priority among the interrupts that are being requested. Finally the

selected interrupt is compared with the processor interrupt priority

level (IPL) contained in the processor status register (PS) and the

request is accepted if it is higher than IPL and the interrupt disable

flag I is “0”. The request is not accepted if flag I is “1”. The reset,

____

DBC, and watchdog timer interrupts are not affected by the inter-

rupt disable flag I.

When an interrupt is accepted, the contents of the processor sta-

tus register (PS) is saved to the stack and the interrupt disable

flag I is set to “1”.

Furthermore, the interrupt request bit of the accepted interrupt is

cleared to “0” and the processor interrupt priority level (IPL) in the

processor status register (PS) is replaced by the priority level of

the accepted interrupt.

Therefore, multi-level priority interrupts are possible by resetting

the interrupt disable flag I to “0” and enable further interrupts.

____

For reset, DBC, watchdog timer, zero divide, and BRK instruction

interrupts, which do not have an interrupt control register, the pro-

cessor interrupt level (IPL) is set as shown in Table 3.

Priority resolution is performed by latching the interrupt request bit

and interrupt priority level so that they do not change. They are

sampled at the first half and latched at the last half of the opera-

tion code fetch cycle.

Because priority resolution takes some time, no sampling pulse is

generated for a certain interval even if it is the next operation code

fetch cycle.

Priority is determined by hardware

4

Ž3

2

1

Watchdog

timer

DBC

Reset

A-D converter, UART, Timer, INT interrupts

Priority can be changed with software inside 4

Fig. 7 Interrupt priority

Level 0

A-D conversion

Interrupt request UART1 transmit

UART1 receive

Reset

UART0 transmit

UART0 receive

Timer B2

Timer B1

DBC

Timer B0

Watchdog

timer

Interrupt disable flag I

Timer A4

Timer A3

Timer A2

Timer A1

Timer A0

INT2

IPL

INT1

INT0

Fig. 8 Interrupt priority resolution

13

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