MC100H641FN 查看數據表（PDF） - Motorola => Freescale
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MC100H641FN Datasheet PDF : 8 Pages
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MC10H641 MC100H641
Using the thermal resistance graph of Figure 2 yields a
thermal resistance of 41°C/W which yields a junction
temperature of 71°C with a range of 56°C to 86°C. Using the
TPD versus Temperature curve of Figure 3 yields a
propagation delay of 5.42ns and a variation of 0.19ns.
Since the design will not experience the full ±5% VCC
variation of the data sheet the 1ns window provided will be
unnecessarily conservative. Using the curve of Figure 4
shows a delay variation due to a ±3% VCC variation of
±0.075ns. Therefore the 1ns window can be reduced to
1ns – (0.27ns – 0.15ns) = 0.88ns. Since H641a and H641b
are on the same board we will assume that they will always be
at the same VCC; therefore the propagation delay window will
only be 1ns – 0.27ns = 0.73ns.
Putting all of this information together leads to a skew
between all devices of
0.19ns + 0.88ns
(temperature + supply, and inherent device),
while the skew between devices A and B will be only
0.19ns + 0.73ns
(temperature + inherent device only).
In both cases, the propagation delays will be centered
around 5.42ns, resulting in the following tPLH windows:
TPLH = 4.92ns – 5.99ns; 1.07ns window
(all devices)
TPLH = 5.00ns – 5.92ns; 0.92ns window
(devices a & b)
Of course the output–to–output skew will be as shown in
the data sheet since all outputs are equally loaded.
This process may seem cumbersome, however the delay
windows, and thus skew, obtained are significantly better than
the conservative worst case limits provided at the beginning
of this note. For very high performance designs, this extra
information and effort can mean the difference between going
ahead with prototypes or spending valuable engineering time
searching for alternative approaches.
Card 1
H641a
Q0
ECL
TTL
Q8
H641b
ECL
Q0
TTL
Q8
H641c
ECL
Card 2
Q0
TTL
Q8
Figure 6. Example Application
MOTOROLA
2–6
MECL Data
DL122 — Rev 6
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