L6256 查看數據表（PDF） - STMicroelectronics

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L6256

12V COMBO

STMicroelectronics 

L6256

UPPER AND LOWER SPINDLE DRIVERS

The spindle drivers provide commutation

switches. Internal inductive flyback protection is

provided, dumping the energy into Vpwr node.

This protection network also provides the energy

transfer to the VCM to allow parking after power

is lost.

The high/low and low/high slew rate of the drivers

during run mode is controlled by the R_Slew pin

to ensure that cross conduction with the lower

drivers does not occur, and that excessive volt-

age slew rates are not produced. Provisions are

made to drive inductive loads due to the possible

filtering requirements. Windings must be damped

with suitable external resistors to allow back EMF

to be detected through the chopping waveform.

INDUCTIVE CLAMP CIRCUIT

The inductive clamp is applied to the motor pins

to prevent the energy from the spindle motor coils

from producing excessive voltages on the part,

when the spindle drivers are tristated or when

commutation occurs.

Back Emf Detect

The back EMF voltage from the spindle motor is

monitored by a sample/hold circuit. First order

slope compensation, set by the value of Rsh and

Csh on the SH_Out pin, is used to reduce jitter.

Sampling will occur during the spindle PWM on

time, and hold during the off time and the

ON_DELAY time. Slope compensation must be

optimized for operation at run speed. During

startup, the zero crossings are detected from all

three phases. During run, only the falling edge of

phase A is useful for timing. A very small amount

of hysteresis is provided to prevent noise glitches.

A fixed offset of approximately Vebias millivolts is

internally introduced to the comparator during

start mode.

The inductive flyback pulse must be masked by

the width of the SP_CLK pulse provided by the

Western Digital controller chip. The width of this

pulse is affected by motor speed and current, as

well as inductance.

Additional back EMF conditioning circuitry is be-

ing provided by Western Digital’s digital controller

chip. The back EMF_Det pin is masked for ap-

proximately 1/4 of the expected commutation cy-

cle, and is latched to prevent multiple transitions.

At power on reset, BEMF_Det is tristated to allow

for in circuit testing.

During run mode, the Ref_In pin sets a prequali-

fier comparator voltage level, which enables the

zero crossing detection circuit about 20µs ahead

of the actual position. Once speed has been sta-

bilized, the spindle phase advance is used to ad-

just the EMF crossing to be coherent with the

6/28

PWM timing. This is done by observing the output

of the preqalifier comparator and comparing it

with the ON_DELAY signal internal to the chip.

This output comparison is provided through the

serial port.

Feedforward Compensation (FFWD Comp)

Any VPWR variations are nulled out by the ra-

tiometric adjustment of the PWM duty cycle. This

circuit converts the fixed processor PWM fre-

quency down to a frequency determined by the

R_Slew resistor and the FF_Comp capacitor.

This frequency is very constant over the entire

specified supply voltage range.

VCM Section

VCM DAC

The VCM DAC buffer brings the VCM_DAC out-

put up to the required drive capability. A 10 bit

monotonic DAC is provided for the VCM.

ATTENUATOR SWITCHES

These provide variable attenuators for the VCM

current control loop, settable from the control reg-

ister. Attenuation settings are cascadable in bi-

nary form, thus requiring 1 bit for each attenuator.

Ratios of 1.5:1, 2:1 and 4:1 give the additional

combinatorial gains of 3:1 (1.5*2), 6:1 (1.5*4), 8:1

(2*4) and 12:1 (all 3 attenuators on simultane-

ously). Attenuator gain ratios are not precisely

controlled relative to one another and differ

slightly between manufacturers.

An overall attenuator enable bit has been added

to the VCM_DAC register address field. If this bit

is a 1 (Combo compatible mode), then the attenu-

ators are enabled. If the bit is a 0, then full gain is

requested. This enables the VCM_DAC write to

accomplish a complete gain shift and DAC write

in a single serial port operation (2 bytes).

LEVEL SHIFT

The level shift circuitry shifts the center voltage of

the VCM current command up to approximately

half of the supply voltage, to provide for symmet-

ric operation of the VCM power amplifiers.

The reference voltage output is a high impedance

input point of approximately Rref ohms to allow

for external bypassing.

VCM AMPLIFIERS

The VCM amplifiers are complementary class AB

output amplifiers, with Bout having higher gain

than the Aout amplifier. This ensures uniform

saturation in either direction.

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