ADSP-21061KSZ-160 查看數據表（PDF） - Analog Devices
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ADSP-21061KSZ-160 Datasheet PDF : 52 Pages
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Clock Input
Table 7. Clock Input
Parameter
Timing Requirements
tCK
tCKL
tCKH
tCKRF
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
ADSP-21061/ADSP-21061L
ADSP-21061
50 MHz, 5 V
ADSP-21061L
44 MHz, 3.3 V
ADSP-21061/
ADSP-21061L
40 MHz,
5 V and 3.3 V
ADSP-21061
33 MHz, 5 V
Min Max Min Max Min Max Min Max Unit
20
100
22.5 100
25
100
30
100
ns
7
7
7
7
ns
5
5
5
5
ns
3
3
3
3
ns
CLKIN
tCKH
tCK
tCKL
Figure 9. Clock Input
Reset
Table 8. Reset
5 V and 3.3 V
Parameter
Min
Max
Unit
Timing Requirements
tWRST
tSRST
RESET Pulse Width Low1
RESET Setup Before CLKIN High2
4tCK
ns
14 + DT/2
tCK
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including startup time of external clock oscillator).
2 Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
RESET
tWRST
tSRST
Figure 10. Reset
Rev. D | Page 21 of 52 | May 2013
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