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5962F9855201QZC 查看數據表(PDF) - Aeroflex UTMC

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产品描述 (功能)
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5962F9855201QZC
UTMC
Aeroflex UTMC 
5962F9855201QZC Datasheet PDF : 62 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Bit Number
Bit 15
Mnemonic
C
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
7
P
Z
N
V
J
IE
MME
RE
OE
Description
Carry. This conditional status is set if a carry is generated
or no borrow. [0]
Carry Equations:
C= (Dm * Sm * Rm) + (Dm * Sm * Rm)
+(Dm * Sm * Rm)
Where: Dm destination register most significant bit
Sm - source register most significant bit
Rm - result most significant bit (stored in
destination register)
Positive. This conditional status is set if the result of an
operation is positive. [0]
Positive Equation: P = N * Z
Zero. This conditional status is set if the result of an
operation is negative. [0]
Zero Equation:Z = Rm * Rm-1 * Rm-2 * R0
Negative. This conditional status is set if the result of an
operation is negative. [0]
Negative Equation: N = Rm
Overflow. This conditional status is set if the result when an
overflow condition occurs. [0]
Overflow Equation:
V = (Dm * Sm * Rm) + (Dm * Sm * Rm)
Normalized. This conditional status is set as the result of a
long instruction and the result is normalized. [0]
Normalized Equation: J = (R32 XOR R31)
Interrupts Enabled. This bit reflects whether interrupts are
disabled or enabled. OTR Rd, ENBL and OTR Rd, DSBL
control this bit and function. [0]
Discrete Input 1. This bit reflects the input stimulus applied
to the input pin.
Receiver Error. This bit is the logical OR combination of the
OE, FE, and PE status bits. [0]
Overrun Error. When active, this bit indicates that at least
one data word was lost because the Data Ready (DR bit 0 of
the Status Register) signal was active twice consecutively
without an INR Rd, RCVR. [0]

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