MSM82C59A-2GS 查看數據表（PDF） - Oki Electric Industry

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MSM82C59A-2GS

PROGRAMMABLE INTERRUPT CONTROLLER

Oki Electric Industry 

¡ Semiconductor

MSM82C59A-2RS/GS/JS

Precautions for operation

Contents: In the case of a cascade edge trigger, the low level width (TILIH) of a slave INT signal

may be less than the low level width (TJLJH:100 ns min.) of a master IR input signal.

This occurs when an interruption request with high order priority is provided to the

slave unit before the INTA cycle ends. Fig.1 shows a system configuration, Fig.2 a bug

operation timing chart, and Fig.3 a normal operation timing chart. TILIH is not

specified.

MSM82C59A-2

MSM82C59A-2

CPU

Master

Slave

IR1 IR1s

INTm

INTR

INT

INTs

INT

IR2 IR2s

INTA

INTA IR7 IR7m

INTA

Fig. 1 System Configuration

IR2S

IR1S

INTA

INTS (IR7m)

INTm

IR2S

IR1S

INTA

INTS (IR7m)

INTm

TILIH (TJLJH) does not satisfy

the spec.

INTS is not accepted.

Fig. 2 Bug Operation Timing Chart

Fig. 3 Normal Operation Timing Chart

TILIH

(TJLJH)

25/28

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