Freescale Semiconductor, Inc. Design Considerations
(A) PDout
VCO
R1
C
(B)
PDout
R1
C
VCO
R2
(C)
φR
φV
R1
R1
C
R2
C
-
A
VCO
+
MC33077 or
R2 equivalent
(Note 3)
ωn =
-K----φ---K-----V----C-----O---
N R1 C
ζ = ---------N-----ω----n-----------
2KφKVCO
F(s) = ------------1-------------
R1sC + 1
ωn =
------K----φ----K----V----C-----O---------
NC(R1 + R2)
ζ
=
0.5
ωn
R2 C
+
-K----φ---K---N--V----C-----O---
F(s)
=
----------R-----2---s----C------+-----1-----------
(R1 + R2)sC + 1
ωn =
-K----φ---K-----V----C-----O---
NCR1
ζ
=
-ω----n----R----2----C---
2
F(s) = R-----2----s---C------+-----1--
R1sC
Notes:
1. For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided
by 2. A capacitor CC is then placed from the midpoint to ground to further filter the error
pulses. The value of CC should be such that the corner frequency of this network does not
significantly affect ωn.
2. The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to
exceed the common mode input range of the op amp.
3. For the latest information on MC33077 or equivalent, see the Motorola IC web site at
http://www.motorola.com/semiconductors.
Denifitions:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = VDD/4p volts per radian for PDout
Kφ (Phase Detector Gain) - VDD/2p volts per radian for fV and fR
KVCO(VCO Gain)
=
2----π----∆----f--V----C-----O---
∆VVCO
For a nominal design starting point, the user might consider a damping factor ζ = 0.7 and a natural loop
frequency ωn = (2πfR/50) where fR is the frequency at the phase detector input. Larger ωn values result
in faster loop lock times and, for similar sideband filtering, higher fR-related VCO standards.
Figure 23. Phase-Locked Loop - Low Pass Filter Design
MOTOROLA
MC145170-2 Technical Data
21
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