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N74374DB 查看數據表(PDF) - Philips Electronics

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N74374DB Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
Latch/flip-flop
Product specification
74F373/74F374
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITION
tsu (H)
tsu (L)
th (H)
th (L)
tw (H)
tsu (H)
tsu (L)
th (H)
th (L)
tw (H)
tw (L)
Setup time, high or low level
Dn to E
Hold time, high or low level
Dn to E
E Pulse width, high
Setup time, high or low level
Dn to CP
Hold time, high or low level
Dn to CP
CP Pulse width,
high or low
74F373
74F374
Waveform 4
Waveform 4
Waveform 1
Waveform 5
Waveform 5
Waveform 5
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
LIMITS
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL= 50pF, RL = 500
MIN TYP MAX
MIN
MAX
0
0
1.0
1.0
3.0
3.0
3.0
3.0
3.5
4.0
2.0
2.0
2.0
2.0
0
0
0
0
3.5
3.5
4.0
4.0
UNIT
ns
ns
ns
ns
ns
ns
CP VM
1/fmax
tw(H)
tPLH
VM
tw(L)
VM
tPHL
Qn
VM
VM
SF00258
Waveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
tw(H)
E VM
VM
tPHL
Qn
VM
VM
tPLH
VM
SF00259
Waveform 2. Propagation delay for enable to output
and enable pulse width
Dn VM
tPLH
VM
tPHL
Qn
VM
VM
SF00260
Waveform 3. Propagation delay for data to output
Dn
VM
VM
tsu(H) th(H)
E
VM
VM
tsu(L)
VM
th(L)
VM
SF00261
Waveform 4. Data setup time and hold times
December 5, 1994
7

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