GENERAL DESCRIPTION
The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) interface device.

FEATURES
• Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)
• Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz
• Meets Bellcore, ANSI and ITU-T specifications
• Meets ITU jitter specification typically to a factor of 2.5
• Integral high-frequency PLL for clock generation
• Interface to TTL logic
• Low jitter PECL (Positive Emitter Coupled Logic) interface
• 4 or 8-bit STM1/OC3 TTL data path
• 4 or 8-bit STM4/OC12 TTL data path
• No external filter components required
• QFP64 package
• Diagnostic and line loopback modes
• Lock detect
• LOS (Loss of Signal) input
• Low power (0.9 W typical)
• Selectable frame detection and byte realignment
• Loop timing
• Forward and reverse clocking
• Squelched clock operation
• Self-biased PECL inputs to support AC coupling.

APPLICATIONS
• SDH/SONET modules
• SDH/SONET-based transmission systems
• SDH/SONET test equipment
• ATM (Asynchronous Transfer Mode) over SDH/SONET
• Add drop multiplexers
• Broadband cross-connects
• Section repeaters
• Fibre optic test equipment
• Fibre optic terminators.