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THC63LVD824A Даташит - THine Electronics, Inc.

THC63LVD824A image

Номер в каталоге
THC63LVD824A

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page
15 Pages

File Size
277.5 kB

производитель
THINE
THine Electronics, Inc. 

General Description
   The THC63LVD824A receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD824A converts the LVDS data streams back into 48bits of CMOS/TTL data with falling edge or rising edge clock for convenient with a variety of LCD panel controllers.

Features
• Wide dot clock range: 25-170MHz suited for VGA,
   SVGA, XGA, SXGA, SXGA+ and UXGA
• PLL requires No external components
• Supports Single Link up to 112MHz dot clock for
   SXGA
• Supports Dual Link up to 170MHz dot clock for
   UXGA
• 50% output clock duty cycle
• TTL clock edge programmable
• TTL output driverbility selectable for lower EMI
• Power down mode
• Low power single 3.3V CMOS design
• 100pin TQFP
• THC63LVDF84B compatible
• Pin compatible with THC63LVD824


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