DESCRIPTION
The ISSI IS61LPS25632T/D/J, IS61LPS25636T/D/J, and IS61LPS51218T/D/J are high-speed, low-power synchronous static RAMs designed to provide burstable, highperformancememory for communication and networking applications. The IS61LPS25632T/D/J is organized as 262,144 words by 32 bits and the IS61LPS25636T/D/J is organized as 262,144 words by 36 bits. The IS61LPS51218T/D/J is organized as 524,288 words by 18 bits.

FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Linear burst sequence control using MODE input
• Three chip enable option for simple depth expansion and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and 119-pin PBGA package
• Power Supply
   +3.3V Vcc
   +3.3V or 2.5 VccQ (I/O)
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• T Version (three chips selects)
• D Version (two chips selects)
• J Version (PBGA Package with JTAG)