GENERAL DESCRIPTION
This EMD56164P is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized as 8,192 rows by 512columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology.
This device uses a double data rate architecture to achieve highspeed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls.
Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

FEATURES
• 1.8V power supply, 1.8V I/O power
• LVCMOS compatible with multiplexed address.
• Double-data-rate architecture; two data transfers per clock
   cycle
• Bidirectional data strobe(DQS)
• Four banks operation.
• MRS cycle with address key programs.
• CAS latency (2, & 3).
• Burst length (2, 4, 8, & 16).
• Burst type (Sequential & Interleave).
• Differential clock inputs(CK and CKB).
• EMRS cycle with address key programs.
• PASR(Partial Array Self Refresh).
• DS (Driver Strength)
• Internal auto TCSR
   (Temperature Compensated Self Refresh)
• Deep power-down(DPD) mode.
• DM for write masking only.
• Auto refresh and self refresh modes.
• 64㎳ refresh period (8K cycle).
• Operating temperature range (-25℃ ~ 85℃).