Functional Description
The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

18-Mbit (512 K × 36/1 M × 18) Flow Through SRAM
Features
■ Supports 133 MHz bus operations
■ 512 K × 36 and 1 M × 18 common I/O
■ 3.3 V core power supply (VDD)
■ 2.5 V or 3.3 V I/O supply (VDDQ)
■ Fast clock-to-output time
   ❐ 6.5 ns (133 MHz version)
■ Provides high performance 2-1-1-1 access rate
■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1381D available in JEDEC-standard Pb-free 100-pin
   TQFP, Pb-free and non Pb-free 165-ball FBGA package.
   CY7C1383D available in JEDEC-standard Pb-free 100-pin
   TQFP. CY7C1383F available in non Pb-free 165-ball FBGA
   package.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option