AD9740 Просмотр технического описания (PDF) - Analog Devices
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AD9740 Datasheet PDF : 32 Pages
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AD9740
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
(MSB) DB9 1
DB8 2
DB7 3
DB6 4
DB5 5
DB4 6
DB3 7
DB2 8
DB1 9
DB0 10
NC 11
NC 12
NC 13
NC 14
AD9740
TOP VIEW
(Not to Scale)
28 CLOCK
27 DVDD
26 DCOM
25 MODE
24 AVDD
23 RESERVED
22 IOUTA
21 IOUTB
20 ACOM
19 NC
18 FS ADJ
17 REFIO
16 REFLO
15 SLEEP
NC = NO CONNECT
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
DB3 1
DB2 2
DVDD 3
DB1 4
DB0 5
NC 6
NC 7
NC 8
PIN 1
INDICATOR
AD9740
TOP VIEW
(Not to Scale)
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
NC = NO CONNECT
Figure 4. 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SOIC/TSSOP LFCSP
Pin No.
Pin No.
Mnemonic
1
27
DB9 (MSB)
2 to 9
28 to 32, 1, 2, 4 DB8 to DB1
10
5
DB0 (LSB)
11 to 14, 19 6 to 9
NC
15
25
SLEEP
16
N/A
REFLO
17
23
REFIO
18
24
FS ADJ
20
19, 22
ACOM
21
20
IOUTB
22
21
IOUTA
23
N/A
RESERVED
24
17, 18
AVDD
25
16
MODE
N/A
15
CMODE
26
10, 26
DCOM
27
3
DVDD
28
N/A
CLOCK
N/A
12
CLK+
N/A
13
CLK−
N/A
11
CLKVDD
N/A
14
CLKCOM
Description
Most Significant Data Bit (MSB).
Data Bits 8 to 1.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active high. Contains active pull-down circuit; it can be
left unterminated if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both
internal and external reference operation modes.
Reference Input/Output. Serves as reference input when using external reference.
Serves as 1.2 V reference output when using internal reference. Requires 0.1 μF capacitor
to ACOM when using internal reference.
Full-Scale Current Output Adjust.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Reserved. Do Not Connect to Common or Supply.
Analog Supply Voltage (3.3 V).
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+
and float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver
(terminations on-chip).
Digital Common.
Digital Supply Voltage (3.3 V).
Clock Input. Data latched on positive edge of clock.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (3.3 V).
Clock Common.
Rev. B | Page 8 of 32
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