STA013 - STA013B - STA013T
Table 5:
PLL Configuration Sequence For
10MHz Input Clock
256 Oversapling Clock
REGISTER
ADDRESS
6
11
97
80
101
82
100
81
5
NAME
reserved
reserved
MFSDF (x)
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
VALUE
18
3
15
16
169
49
42
60
161
Table 6:
PLL Configuration Sequence For
10MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
6
11
97
80
101
82
100
81
5
NAME
reserved
reserved
MFSDF (x)
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
VALUE
17
3
9
10
110
160
152
186
161
Table 7:
PLL Configuration Sequence For
14.31818MHz Input Clock
256 Oversapling Rathio
REGISTER
ADDRESS
6
11
97
80
101
82
100
81
5
NAME
reserved
reserved
MFSDF (x)
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
VALUE
12
3
15
16
187
103
58
119
161
Table 8:
PLL Configuration Sequence For
14.31818MHz Input Clock
384 Oversapling Rathio
REGISTER
ADDRESS
6
11
97
80
101
82
100
81
5
NAME
reserved
reserved
MFSDF (x)
MFSDF-441
PLLFRAC-H
PLLFRAC-441-H
PLLFRAC-L
PLLFRAC-441-L
PLLCTRL
VALUE
11
3
6
7
3
157
211
157
161
32/38