ADSP-2162KS-40_ Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADSP-2162KS-40_

DSP Microcomputers with ROM

Analog Devices 

ADSP-216x

CLKIN

XTAL

ADSP-216x

CLKOUT

Figure 2. External Crystal Connections

A clock output signal (CLKOUT) is generated by the processor,

synchronized to the processor’s internal cycles.

Reset

The RESET signal initiates a complete reset of the ADSP-216x.

The RESET signal must be asserted when the chip is powered

up to assure proper initialization. If the RESET signal is applied

during initial power-up, it must be held long enough to allow

the processor’s internal clock to stabilize. If RESET is activated

at any time after power-up and the input clock frequency does

not change, the processor’s internal clock continues and does

not require this stabilization time.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid VDD is

applied to the processor and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 tCK cycles will ensure that the PLL has locked (this does

not, however, include the crystal oscillator start-up time).

During this power-up sequence the RESET signal should be

held low. On any subsequent resets, the RESET signal must

meet the minimum pulsewidth specification, tRSP.

To generate the RESET signal, use either an RC circuit with an

external Schmidt trigger or a commercially available reset IC.

(Do not use only an RC circuit.)

The RESET input resets all internal stack pointers to the empty

stack condition, masks all interrupts, and clears the MSTAT

register. When RESET is released, the boot loading sequence is

performed (provided there is no pending bus request and the chip

is configured for booting, with MMAP = 0). The first instruction is

then fetched from internal program memory location 0x0000.

PIN FUNCTION DESCRIPTIONS

Pin

Name(s)

Address

Data1

# of

Pins

14

24

RESET

1

IRQ2

1

BR2

1

BG

1

PMS

1

DMS

1

BMS

1

RD

1

WR

1

MMAP

1

CLKIN, XTAL

2

CLKOUT

1

VDD

GND

SPORT0

5

SPORT1

5

or Interrupts and Flags:

IRQ0 (RFS1)

1

IRQ1 (TFS1)

1

FI (DR1)

1

FO (DT1)

1

PWDACK3

1

PWDFLAG3

1

NOTES

1Unused data bus lines may be left floating.

2BR must be tied high (to VDD) if not used.

3Only on ADSP-2165/ADSP-2166.

Input/

Output

O

I/O

I

I

I

O

O

O

O

O

O

I

I

O

I/O

I/O

I

I

I

O

O

I

Function

Address outputs for program, data and boot memory.

Data I/O pins for program and data memories. Input only for

boot memory, with two MSBs used for boot memory addresses.

Unused data lines may be left floating.

Processor Reset Input

External Interrupt Request #2

External Bus Request Input

External Bus Grant Output

External Program Memory Select

External Data Memory Select

Boot Memory Select

External Memory Read Enable

External Memory Write Enable

Memory Map Select Input

External Clock or Quartz Crystal Input

Processor Clock Output

Power Supply Pins

Ground Pins

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

External Interrupt Request #0

External Interrupt Request #1

Flag Input Pin

Flag Output Pin

Indicates when the processor has entered power-down.

Low-to-High Transition of the Power-Down Flag. Input pin can

be used to terminate power-down.

–6–

REV. 0

Share Link: