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PI6C3Q993A-5IQ Просмотр технического описания (PDF) - Pericom Semiconductor

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производитель
PI6C3Q993A-5IQ
Pericom-Semiconductor
Pericom Semiconductor 
PI6C3Q993A-5IQ Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PI6C3Q991A, PI6C3Q993A
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221132233.34455V667788P9900r11o22g3344r55a6677m8899m001122a3344b55l66e7788S9900k1122e11w223344P5566L7788L9900C1122l33o4455c66k778899D0011r22i33v4455e66r7788S9900u11p2211e22r33C4455l66o7788c99k001122
Table 10. Input Timing Requirements(22)
Symbol
Description
Min.
Max.
Units
tR, tF
Maximum input rise and fall times, 0.8V to 2.0V
10
ns/V
tPWC
Input clock pulse, HIGH or LOW
3
ns
DH
Input duty cycle
10
90
%
Notes:
22. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is less than tPWC limit,
tPWC limit applies.
REF
tREF
tRPWH
tRPWL
tPD
FB
tODCV tODCV
tJR
Q
Other Q
ttSSKKEEWW0P, R1
ttSSKKEEWW0P, R1
tSKEW2
tSKEW2
Inverted Q
REF Divided by 2
tSKEW3,4
tSKEW3,4
tSKEW3,4
tSKEW1,3,4
tSKEW2,4
REF Divided by 4
Figure 2. AC Timing Diagram
Notes:
VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the
negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2
and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same tU delay has been
selected when all are loaded with 20pF and terminated with 75ohms to VCC/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0: The skew between outputs when they are selected for 0t U.
tDEV: The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature,
air flow, etc.)
tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4
specifications.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until
tPD is within specified limits.
tPWH is measured at 2.0V.
tPWL is measured at 0.8V.
tORISE & tOFALL
are measured between 0.8V and 2.0V.
8
PS8628 08/15/02

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