LTC6992HS6-4-WTRMPBF Просмотр технического описания (PDF) - Analog Devices

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LTC6992HS6-4-WTRMPBF

TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)

Analog Devices 

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

PIN FUNCTIONS (DCB/S6)

V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This

sup-ply should be kept free from noise and ripple. It

should be bypassed directly to the GND pin with a 0.1μF

capacitor.

DIV (Pin 2/Pin 4): Programmable Divider and Polarity

Input. The DIV pin voltage (VDIV) is internally converted

into a 4-bit result (DIVCODE). VDIV may be generated by

a resistor divider between V+ and GND. Use 1% resistors

to ensure an accurate result. The DIV pin and resistors

should be shielded from the OUT pin or any other traces

that have fast edges. Limit the capacitance on the DIV pin

to less than 100pF so that VDIV settles quickly. The MSB of

DIVCODE (POL) determines if the PWM signal is inverted

before driving the output. When POL = 1 the transfer func-

tion is inverted (duty cycle decreasing as VMOD increases).

SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage

on the SET pin (VSET) is regulated to 1V above GND. The

amount of current sourced from the SET pin (ISET) pro-

grams the master oscillator frequency. The ISET current

range is 1.25μA to 20μA. The output oscillation will stop

if ISET drops below approximately 500nA. A resistor con-

nected between SET and GND is the most accurate way to

set the frequency. For best performance, use a precision

metal or thin film resistor of 0.5% or better tolerance

and 50ppm/°C or better temperature coefficient. For lower

accuracy applications an inexpensive 1% thick film resis-

tor may be used.

Limit the capacitance on the SET pin to less than 10pF

to minimize jitter and ensure stability. Capacitance less

than 100pF maintains the stability of the feedback circuit

regulating the VSET voltage.

V+

MOD OUT

LTC6992

GND

V+

SET

RSET

DIV

6992 PF

V+

C1

0.1µF R1

R2

MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The

voltage on the MOD pin controls the output duty cycle. The

linear control range is between 0.1 • VSET and 0.9 • VSET

(approximately 100mV to 900mV). Beyond those limits,

the output will either clamp at 5% or 95%, or stop oscil-

lating (0% or 100% duty cycle), depending on the version.

GND (Pin 5/Pin 2): Ground. Tie to a low inductance

ground plane for best performance.

OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings

from GND to V+ with an output resistance of approximately

30Ω. The duty cycle is determined by the voltage on the

MOD pin. When driving an LED or other low-impedance

load a series output resistor should be used to limit the

source/sink current to 20mA.

For more information www.analog.com

Rev. D

13

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