DS2181A Просмотр технического описания (PDF) - Maxim Integrated

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производитель

DS2181A

CEPT Primary Rate Transceiver

Maxim Integrated 

RECEIVE MULTIFRAME BOUNDARY TIMING Figure 17

DS2181A

NOTES:

1. Low-high transitions on RMSYNC and RFSYNC occur one RCLK period early with respect to actual

frame and multiframe boundaries.

2. RAF transitions on true frame boundaries.

3. Delay from RPOS, RNEG to RSER is six RCLK periods.

4. RMSYNC and RCSYNC transition low on the falling edge of RFSYNC.

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