MITSUBISHI LSIs
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM
Burst Mode Address
Initial Address
Sequential
Interleaved
BL
As2 As1 As0
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 00
01 2 34 5 67 01 2 345 6 7
0 01
1 2 34 5 67 010 3 25 4 76
0 10
2 34 5 67 01 23 0 16 7 45
0 11
34 5 67 01 232 1 07 6 54
8
1 00
4 5 67 01 2 345 6 70 1 23
1 01
5 67 01 2 34 54 7 61 0 32
1 10
67 01 2 34 567 4 52 3 01
1 11
7 01 2 34 5 676 5 43 2 10
0 00
01 2 3
01 2 3
- 01
1 2 30
4
- 10
2 3 01
10 3 2
23 0 1
- 11
3 01 2
32 1 0
- -0
01
2
- -1
10
01
10
Note: When SRAM command is executed more than burst length, the Address
repeats with the same sequence.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
63