M5M4V16169DRT-7 Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M5M4V16169DRT-7

16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

M5M4V16169DTP/RT-7,-8,-10,-15

16MCDRAM:16M(1M-WORD BY 16-BIT) CACHED DRAM WITH 16K (1024-WORD BY 16-BIT) SRAM

DRAM Write Transfer 1 (WB1->WB2->DRAM)

Buffer Write (DIN->WB1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

K

tRC

CMd#

CS#

RAS#

CAS#

tRP

tRAS

tRCD

tRWL

DTD#

Ad0-2

Ad3-11

Row

Row

Ad0-Ad2=Low

**Col

WB2

WB1

Old Data

New Data[WB1(0-7)]

C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4

DRAM

SRAM

DPD DPD PCG DPD DPD DPD ACT DNOP DWT1 DNOP PCG DPD DPD DPD

DES BW BW BW BW BW BW BW BW BW BW BW BW BW

DQ0-15

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5

Please refer to next page in detail.

SRAM operation can be freely performed.

MITSUBISHI ELECTRIC

** Ad3-Ad7 are column block addresses (Ad8~Ad11=Low).

(REV 1.0) Jul. 1998

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