SPC5605BF1CLQ6 Просмотр технического описания (PDF) - Freescale Semiconductor
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SPC5605BF1CLQ6 Datasheet PDF : 110 Pages
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Package pinouts and signal descriptions
3.3 Pad configuration during standby mode exit
Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled by both the SIUL and WKPU
modules. During standby exit, all low power pads PA[0,1,2,4,15], PB[1,3,8,9,10]1, PC[7,9,11], PD[0,1], PE[0,9,11],
PF[9,11,13]2, PG[3,5,7,9]2, PI[1,3]3 are configured according to their respective configuration done in the WKPU module. All
other pads will have the same configuration as expected after a reset.
The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY
mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an
input. When no debugger is connected the TDO pad is floating causing additional current consumption.
To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47–100 kOhms should be
added between the TDO pin and VDD. Only if the TDO pin is used as an application pin and a pull-up cannot be used should
a pull-down resistor with the same value be used instead between the TDO pin and GND.
3.4 Voltage supply pins
Voltage supply pins are used to provide power to the device. Three dedicated VDD_LV/VSS_LV supply pairs are used for 1.2 V
regulator stabilization.
Table 3. Voltage supply pin descriptions
Port pin
Function
100 LQFP
Pin number
144 LQFP 176 LQFP 208 MAPBGA
VDD_HV Digital supply voltage
15, 37, 70, 84 19, 51, 100, 6, 27, 59, 85, C2, D9, E16,
123
124, 151 G13, H3, N4,
N9, R5
VSS_HV Digital ground
14, 16, 35, 69, 18, 20, 49, 99,
83
122
7, 26, 28, 57,
86, 123, 150
G7, G8, G9,
G10, H7, H8,
H9, H10, J7,
J8, J9, J10,
K7, K8, K9,
K10
VDD_LV
VSS_LV
VDD_BV
1.2 V decoupling pins. Decoupling
capacitor must be connected
between these pins and the nearest
VSS_LV pin.1
1.2 V decoupling pins. Decoupling
capacitor must be connected
between these pins and the nearest
VDD_LV pin.1
Internal regulator supply voltage
19, 32, 85
18, 33, 86
20
23, 46, 124 31, 54, 152 D8, K4, P7
22, 47, 125 30, 55, 153 C8, J2, N7
24
32
K3
VSS_HV_ADC0 Reference ground and analog ground
51
73
89
R15
for the A/D converter 0 (10-bit)
VDD_HV_ADC0 Reference voltage and analog supply
52
74
90
P14
for the A/D converter 0 (10-bit)
VSS_HV_ADC1 Reference ground and analog ground
59
81
98
N12
for the A/D converter 1 (12-bit)
1. PB[8, 9] ports have wakeup functionality in all modes except STANDBY.
2. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.
3. PI[1,3] are not available in the 144-pin LQFP.
MPC5607B Microcontroller Data Sheet, Rev. 6
12
Freescale Semiconductor
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