CY62167EV18LL(2011) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62167EV18LL Datasheet PDF : 16 Pages
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Truth Table
CE1 CE2 WE
H X[30] X
X[30] L
X
X[30] X[30] X
L HH
L HH
L HH
L HH
L HH
L HH
LHL
LHL
LHL
OE BHE BLE
Inputs/Outputs
X X X High Z
X X X High Z
X H H High Z
L
L
L Data Out (I/O0–I/O15)
L H L Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
L
L
H High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
H L H High Z
H H L High Z
H L L High Z
X
L
L Data In (I/O0–I/O15)
X H L Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
X L H High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
CY62167EV18 MoBL®
Mode
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read
Read
Read
Output disabled
Output disabled
Output disabled
Write
Write
Write
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
30. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document #: 38-05447 Rev. *L
Page 10 of 16
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