AD7175-8 Просмотр технического описания (PDF) - Analog Devices

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AD7175-8

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers

Analog Devices 

AD7175-8

Data Sheet

Bits Bit Name Settings Description

3

OP_EN1

This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS.

0 Disabled.

1 Enabled.

2

OP_EN0

This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS.

0 Disabled.

1 Enabled.

1

GP_DATA1

This bit is the readback or write data for GPIO1.

0

GP_DATA0

This bit is the readback or write data for GPIO0.

ID REGISTER

Address: 0x07, Reset: 0x3CDx, Name: ID

The ID register returns a 16-bit ID. For the AD7175-8, this ID is 0x3CDx.

Reset

0x0

0x0

0x0

0x0

Access

RW

RW

RW

RW

Table 32. Bit Descriptions for ID

Bits Bit Name

Settings

[15:0] ID

0x3CDx

Description

The ID register returns a 16-bit ID code that is specific to the ADC.

AD7175-8

Reset Access

0x3CDx R

CHANNEL REGISTER 0

Address: 0x10, Reset: 0x8001, Name: CH0

The channel registers are 16-bit registers used to select which channels are currently active, which inputs are selected for each channel,

and which setup is used to configure the ADC for that channel.

Table 33. Bit Descriptions for CH0

Bits Bit Name

Settings

15

CH_EN0

0

1

[14:12] SETUP_SEL0

[11:10] RESERVED

[9:5] AINPOS0

000

001

010

011

100

101

110

111

00000

00001

00010

00011

00100

00101

00110

00111

Description

This bit enables Channel 0. If more than one channel is enabled, the ADC

automatically sequences between them.

Disabled

Enabled (default)

These bits identify which of the eight setups is used to configure the

ADC for this channel. A setup comprises a set of four registers: setup

configuration register, filter configuration register, offset register, and gain

register. All channels can use the same setup, in which case the same 3-bit

value must be written to these bits on all active channels, or up to eight

channels can be configured differently.

Setup 0

Setup 1

Setup 2

Setup 3

Setup 4

Setup 5

Setup 6

Setup 7

These bits are reserved; set these bits to 0.

These bits select which input is connected to the positive input of the

ADC for this channel.

AIN0 (default)

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

Reset

0x1

0x0

0x0

0x0

Access

RW

RW

R

RW

Rev. 0 | Page 56 of 64

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