ISL29013IROZ-T7 Просмотр технического описания (PDF) - Renesas Electronics
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ISL29013IROZ-T7
Renesas Electronics
ISL29013IROZ-T7 Datasheet PDF : 14 Pages
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ISL29013
Register Set
There are eight registers that are available in the ISL29013. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET
BIT
ADDR REG NAME
7
6
5
4
3
2
1
0
DEFAULT
00h COMMAND ADCE
ADCPD
TIMM
0
ADCM1 ADCM0
RES1
RES0
00h
01h
CONTROL
0
0
INT_FLAG
0
GAIN1
GAIN0
IC1
IC0
00h
02h
Interrupt
ITH_HI7 ITH_HI6 ITH_HI5 ITH_HI4
ITH_HI3 ITH_HI2 ITH_HI1 ITH_HI0
FFh
Threshold_HI
03h
Interrupt ITH_LO7 ITH_LO6 ITH_LO5 ITH_LO4 ITH_LO3 ITH_LO2 ITH_LO1 ITH_LO0
00h
Threshold_LO
04h LSB SENSOR S7
S6
S5
S4
S3
S2
S1
S0
00h
05h
MSB
S15
S14
S13
S12
S11
S10
S9
S8
00h
SENSOR
06h LSB TIMER
T7
T6
T5
T4
T3
T2
T1
T0
00h
07h MSB TIMER
T15
T14
T13
T12
T11
T10
T9
T8
00h
TABLE 2. WRITE ONLY REGISTERS
REGISTER
ADDRESS NAME
FUNCTIONS/
DESCRIPTION
b1xxx_xxxx sync_I2C Writing a logic 1 to this address bit ends the
current ADC-integration and starts another.
Used only with External Timing Mode.
bx1xx_xxxx clar_int Writing a logic 1 to this address bit clears
the interrupt.
Command Register 00(hex)
The Read/Write command register has five functions:
1. Enable; Bit 7.This function either resets the ADC or enables
the ADC in normal operation. A logic 0 disables ADC to reset-
mode. A logic 1 enables ADC to normal operation.
TABLE 3. ENABLE
BIT 7
OPERATION
0
disable ADC-core to reset-mode (default)
1
enable ADC-core to normal operation
2. ADCPD; Bit 6. This function puts the device in a power
down mode. A logic 0 puts the device in normal operation.
A logic 1 powers down the device.
TABLE 4. ADCPD
BIT 6
OPERATION
0
Normal operation (default)
1
Power Down
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an internal
dual speed oscillator (fOSC), and the n-bit (n = 4, 8, 12,16)
counter inside the ADC. In External Timing Mode,
integration time is determined by the time between three
consecutive external-sync sync_I2C pulses commands.
BIT 5
0
1
TABLE 5. TIMING MODE
OPERATION
Internal Timing Mode. Integration time is internally timed
determined by fOSC, REXT, and number of clock cycles.
External Timing Mode. Integration time is externally
timed by the I2C host.
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and Bit
2 to 1 and 0 enables ADC to give light count DATA output.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BITS 3:2
MODE
0:0 Disable ADC
0:1 Disable ADC
1:0 Light count DATA output in signed (n-1) bit *
1:1 No operation.
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
5. Width; Bits 1 and 0. This function determines the number of
clock cycles per conversion. Changing the number of clock
cycles does more than just change the resolution of the
device. It also changes the integration time, which is the
period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
measurement.
.
TABLE 7. WIDTH
BITS 1:0
0:0
0:1
1:0
1:1
NUMBER OF CLOCK CYCLES
216 = 65,536
212 = 4,096
28 = 256
24 = 16
FN6485 Rev 3.00
November 11, 2011
Page 5 of 14
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