PEB2047-N Просмотр технического описания (PDF) - Infineon Technologies

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PEB2047-N

Memory Time Switch Large

Infineon Technologies 

PEB 2047

PEB 2047-16

3.5 Input Offset and Output Offset

Based on the results of the frame evaluation procedures the input offsets can be adjusted by

programming ICSR (7:0) corresponding to inputs IN (7:0). If data oversampling is used, the values

of ICSR (7:0) can be adjusted within some limits during operation without producing bit errors:

a) clockrate = 2 × datarate

possible adjustment is one half clockperiod forward or backward.

Data

CLK

ITD03774

-

1

2

0

+

1

2

Figure 10

b) clockrate = 4 × datarate

possible adjustment is one clockperiod backward or two clockperiods forward.

Data

CLK

ITD03775

-1

-

1

2

0

0

+

1

2

+1

+

3

2

+2

Figure 11

The output offset is the same for all output lines and is fixed in register OCSR.

Semiconductor Group

20

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