74LVC1G53DC Просмотр технического описания (PDF) - Nexperia B.V. All rights reserved

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производитель

74LVC1G53DC

2-channel analog multiplexer/demultiplexer

Nexperia B.V. All rights reserved 

Nexperia

74LVC1G53

2-channel analog multiplexer/demultiplexer

Y0

S

Z

Y1

E

Figure 2.  Logic diagram

6 Pinning information

001aad387

6.1 Pinning

74LVC1G53

Z1

8 VCC

E2

7 Y0

74LVC1G53

Z1

E2

GND 3

GND 4

8 VCC

7 Y0

6 Y1

5S

001aad388

Figure 3.  Pin configuration SOT505-2 and SOT765-1

GND 3

6 Y1

GND 4

5S

001aad389

Transparent top view

Figure 4.  Pin configuration SOT833-1, SOT1089,

SOT1116 and SOT1203

74LVC1G53

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 11 — 16 January 2018

© Nexperia B.V. 2018. All rights reserved.

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